Verilog MCQ Questions

Verilog MCQ Questions

  • Satyam Jaiswal
  • 22nd May, 2021

We are introducing here the best Verilog MCQ Questions, which are very popular & asked various times. This Quiz contains the best 25+ Verilog MCQ with Answers, which cover the important topics of Verilog so that, you can perform best in Verilog exams, interviews, and placement activities.

Best Verilog MCQ Questions

1) Who developed the Verilog?

  • A. Moorby
  • B.Ritchie
  • C.Moorby and Thomson
  • D.Russell and Ritchie

2) The Verilog is a hardware description language

  • A. hardware description language
  • B.software description language
  • C.hardware decision language
  • D.software decision language

3) In which year the Verilog was developed?

  • A. 1992
  • B.1991
  • C.1889
  • D.1888

4) The Verilog is modelled for the ________ devices.

  • A. condution
  • B.electrical
  • C.electronics
  • D.All of the above

5) ______ versions of the Verilog is known as System Verilog.

  • A. Verilog version 1.0
  • B.Verilog version 4.0
  • C.Verilog version 2.0
  • D.Verilog version 3.0

6) The _________ is the first version of the Verilog.

  • A. IEEE standard 1364-1994
  • B.IEEE standard 1364-2000
  • C.IEEE standard 1364-1995
  • D.IEEE standard 1364-1997

7) The _________ is the version of the Verilog 2.0.

  • A. IEEE standard 1364-2001
  • B.IEEE standard 1364-2000
  • C.IEEE standard 1364-1995
  • D.IEEE standard 1364-1997

8) ________ provides multiple-valued logic with eight signal strength.

  • A. C
  • B.Verilog
  • C.C++
  • D.Java

9) _______ is a superset of Verilog.

  • A. Verilog
  • B.System Verilog
  • C.VHDL
  • D.System VHDL

10) _______ is a superset of Verilog.

  • A. Verilog
  • B.System Verilog
  • C.VHDL
  • D.System VHDL

11) _________ hardware description language is more flexible.

  • A. C
  • B.Java
  • C.Verilog
  • D.VHDL

12) Which is wrong?

  • A. The Verilog supports the multiple-valued logic.
  • B.The Verilog is more flexible compared to the VHDL
  • C.The Verilog is less flexible compared to the VHDL.
  • D.None of the above

13) The Verilog offers more features than the VHDL.

  • A. True
  • B.False

14) The Verilog can provide transistor-level descriptions but the VHDL cannot provide this description.

  • A. Yes
  • B.No
  • C.May be
  • D.Can't say

15) The Verilog can provide transistor-level descriptions but the VHDL cannot provide this description.

  • A. Yes
  • B.No
  • C.May be
  • D.Can't say

16) __________ hardware description language is popular in the US.

  • A. System Verilog
  • B.Verilog
  • C.System VDHL
  • D.VDHL

17) VDHL hardware description language is popular in the _________.

  • A. Canada
  • B.US
  • C.Europe
  • D.None of the above

18) Operator which precedes the operand is known as __________.

  • A. Unary
  • B.Binary
  • C.Ternary
  • D.None of the above

19) ________ command is used to suspend a simulation.

  • A. $finish
  • B.$suspend
  • C.$stop
  • D.None of the above

20) ________ operator is used to trigger an event.

  • A. @
  • B.&
  • C.$$
  • D.==

21) In continuous assignment statement LHS can be _________.

  • A. Vector net
  • B.Scalar net Vector net
  • C.Concatenation of both
  • D.All of the above

22) ________ is used to introduce delays in a circuit.

  • A. Flip-flops
  • B.EXOR gate
  • C.Inverter
  • D.Buffer

23) Arrays are not allowed for _________.

  • A. characters
  • B.time
  • C.real
  • D.bool

24) @posedge means ________ .

  • A. Transition from 0 to 1,x or z
  • B.Transition from x to 1
  • C.Transition from z to 1
  • D.Transition from z to x

25) What is the width of time register?

  • A. 16 bit
  • B.32 bit
  • C.64 bit
  • D.128 bit

26) The wait statement is _________.

  • A. edge sensitive
  • B.level sensitive
  • C.Both A and B
  • D.None of the above

27) The possible values of the == operator are __________.

  • A. 0
  • B.1
  • C.x
  • D.All of the above

28) The default value for reg data type is ______.

  • A. 0
  • B.1
  • C.x
  • D.z

29) __________ is used to overwrite the value of a parameter during module instantiation.

  • A. `ifdef
  • B.`timescale
  • C.`define
  • D.`include

30) ______ defines special parameters in the specify block.

  • A. specparam
  • B.param
  • C.defparam
  • D.parameter

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